1. Field of the Invention
The present invention relates generally to wafer polishing and, more specifically, to a Chemical Mechanical Polishing (CMP) pad dresser used in lapping and polishing silicon wafers in either single or double sided polishing machines.
Chemical Mechanical Polishing (CMP) is a process that is used for the planarization of semiconductor wafers. CMP takes advantages of the synergetic effect of both physical and chemical forces for polishing of wafers. This is done by applying a load force to the back of a wafer while it rests on a pad. Both the pad and wafer are then counter rotated while a slurry containing both abrasives and reactive chemicals is passed underneath.
The goal of CMP is to obtain uniform planarization globally across the wafer. The wafers consist of many small dies and patterns, which take the form of interconnected lines of copper and silica. Planarization occurs when the interconnects are polished to the point where both the copper and the silica lines are at the same level.
CMP has emerged as the dominant dielectric planarization method due to its ability to reduce topography over longer lateral distances than earlier techniques. However, CMP still suffers from pattern dependencies that result in large variation in polished oxide thickness across typical chips, which can impact circuit performance and yield. The present invention improves upon CMP process resulting in improved planarization and thus improved performance and higher yield.
The present invention is a chemical mechanical polishing pad dresser, conditioners or groomers consisting of several integrated pieces and design components, layered in a sandwich type design.
The apparatus of the present invention consists of a bottom layer of fiberglass or other suitable material with round cavities or pockets machined into the surface of the material in various patterns and a top layer of the same material with holes matching the locations of the bottom layer cavities or pockets. The bottom layer has double side glue tape applied with a protective backing shield that is peeled off at mounting, thus allowing the tool to be easily attached to the polishing machine head or carrier. The matching round holes in the top layer are of slightly smaller diameter than the bottom layer cavities to permanently hold or contain the spinning islands or discs in the cavities upon assembly of the various layers. Mylar shims are placed in the bottom layer cavities and the spinning polishing islands are placed in the cavities or pockets on top of the shims. The shims facilitate the spinning of the polishing discs or islands, which are slightly less diameter that the cavity diameters to further facilitate the spinning feature. The top layer with the machining holes is glued to the bottom layer, thereby permanently containing the spinning islands in the pockets or cavities.
The round layers are designed and may be suited to the same diameter as any polishing machine head and can be utilized by either single or double sided polishing machines.
2. Description of the Prior Art
There are other methods and apparatuses for polishing silicon wafers. Typical of these is U.S. Pat. No. 4,165,584 was issued to Scherrer on Aug. 28, 1979
Another patent was issued to Budinger on Apr. 23, 1985 as U.S. Pat. No. 4,512,113. Yet another U.S. Pat. No. 5,647,789 was issued to Kitta on Jul. 15, 1997 and still yet another was issued on Oct. 16, 1990 to Wydle as U.S. Pat. No. 4,962,618.
Another patent was issued to Nakazima on Nov. 12, 1996 as U.S. Pat. No. 5,573,448. Yet another U.S. Pat. No. 5,788,560 was issued to Hashimoto on Aug. 4, 1998. Another was issued to Nguyen on Sep. 2, 2003 as U.S. Pat. No. 6,612,905
Still yet another was issued on Nov. 11, 2003 to Nguyen as U.S. Pat. No. 6,645,049. Another patent was issued to Nguyen on Dec. 23, 2003 as U.S. Pat. No. 6,666,948. Yet another U.S. Pat. No. 6,733,367 was issued to Nguyen on May 11, 2004.